1. Field of the Invention
This invention relates to a semiconductor device, and especially relates to a semiconductor device comprising a signal line in which a voltage higher than the voltage supply is generated.
2. Description of the Prior Art
Recently, the voltage supply V.sub.CC of a dynamic RAM (Random Access Memory) using MOS transistors has been lowered by degrees, and is in general V.sub.CC =5 V. However, the electric charge accumulated in the memory cell in the case of V.sub.CC =5 V is less than that in the case of V.sub.CC =12 V or another higher voltage. Accordingly, the charging condition in the memory cell in the case of V.sub.CC =5 V is disadvantageous for carrying out a refresh action and is apt to be influenced by .alpha.-rays and so on, and therefore it becomes necessary to generate a voltage higher than the voltage supply V.sub.CC at the signal line by using a bootstrap circuit, a push-up circuit, or another type of circuit in order to utilize the V.sub.CC level as much as possible.
A dynamic RAM semiconductor device in which a push-up circuit is used for the above-mentioned purpose is illustrated in FIG. 1. As illustrated in FIG. 1, this device has a push-up circuit PU, a precharger circuit PRE for the pair of bit lines BL and BL which are driven by the output of the push-up circuit PU, and the sense amplifier circuit SA for the memory cells. FIG. 2 illustrates various voltage waveforms used to explain the operation of the push-up circuit PU of FIG. 1.
The push-up circuit PU consists of transistors Q.sub.1 and Q.sub.2, a push-up capacitor C.sub.1 and an output signal line S.sub.1 as illustrating in FIG. 1. A clock signal .phi..sub.1 is applied as an input to the gate of the transistor Q.sub.1 and another clock signal .phi..sub.2 is applied to the gate of the transistor Q.sub.2. As illustrated in FIG. 2, at first, the clock .phi..sub.1 is at the L(low) level and the clock .phi..sub.2 is at the H(high) level so that the transistor Q.sub.1 is OFF and the transistor Q.sub.2 is ON; therefore, the level of the output signal line S.sub.1 is kept at the L level (V.sub.SS). Then, the clock .phi..sub.2 falls to the L level to turn off the transistor Q.sub.2 ; after that, the clock .phi..sub.1 rises to the H level (higher than V.sub.CC) to fully turn on the transistor Q.sub.1 so that the signal line S.sub.1 is charged up to the V.sub.CC level. Under this condition, the clock .phi..sub.1 falls to the L level to turn off the transistor Q.sub.1, and therefore the signal line S.sub.1 is cut off from the voltage supply line V.sub.cc. Then, the clock .phi..sub.3 rises from the L level (V.sub.SS) to the H level (V.sub.CC) so that the level of the signal line S.sub.1 is pushed up to a level V.sub.S1 higher than the voltage supply V.sub.CC through the capacitor C.sub.1.
This voltage level V.sub.S1 of the signal line S.sub.1 is applied as an input to the precharger circuit PRE. As illustrated in FIG. 1, the precharger circuit PRE consists of transistors Q.sub.3, Q.sub.4 and Q.sub.5. The signal line S.sub.1 is connected to all the gates of the transistors Q.sub.3, Q.sub.4 and Q.sub.5. The drains of the transistors Q.sub.3 and Q.sub.4 are connected to the voltage supply V.sub.CC, and the sources of the transistors Q.sub.3 and Q.sub.4 are connected to the pair of bit lines BL and BL, respectively. The drain and source of the transistor Q.sub.5 are connected to the pair of bit lines BL and BL, respectively.
The sense amplifier circuit SA consists of transistors Q.sub.6, Q.sub.7 and Q.sub.8 as illustrated in FIG. 1. The drain of the transistor Q.sub.6 and the gate of the transistor Q.sub.7 are both connected to one line BL of the pair of bit lines, and the gate of the transistor Q.sub.6 and the drain of the transistor Q.sub.7 are both connected to another line BL of the pair of bit lines. The sources of the transistors Q.sub.6 and Q.sub.7 are both connected to the drain of the transistor Q.sub.8, and the source of the transistor Q.sub.8 is connected to the reference voltage V.sub.SS. The clock signal .phi..sub.4 is applied to the gate of the transistor Q.sub.8.
Transistors Q.sub.9, Q.sub.9 ' . . . of the memory cells MC corresponding to the word lines WL.sub.1, WL.sub.1 ' . . . are all connected to one line BL of the pair of bit lines, and transistors Q.sub.10, Q.sub.10 ' . . . of the memory cells MC corresponding to the word lines WL.sub.2, WL.sub.2 ' . . . are all connected to another line BL of the pair of bit lines. For example, if the content of the memory cell MC including the transistor Q.sub.9 is "1" and the word line WL.sub.1 is selected, when the clock .phi..sub.4 rises from the L level to the H level to turn on the transistor Q.sub.8, the sense amplifier circuit SA operates to turn off the transistor Q.sub.6 and to turn on the transistor Q.sub.7 so that the levels of the pair of bit lines are BL=H and BL=L. And if the content of the above-mentioned memory cell MC is "0", then the circuit SA operates to turn on the transistors Q.sub.6 and to turn off the transistor Q.sub.7 so that the levels of the pair of bit lines are BL=L and BL=H.
In the sense amplifier circuit SA, preceding the above-mentioned sense action, it is necessary to precharge the pair of bit lines BL and BL so as to make the potentials of the pair of bit lines BL and BL equal to each other. In order to do so, when the clock .phi..sub.1 rises to the H level as illustrated in FIG. 2, the gate voltages of the transistors Q.sub.3, Q.sub.4 and Q.sub.5 rise to the V.sub.CC level through the signal line S.sub.1 and the pair of bit lines BL and BL are charged up from the voltage supply V.sub.CC through the transistors Q.sub.3 and Q.sub.4, respectively. The transistor Q.sub.5 is connected between the pair of bit lines BL and BL, and it becomes conductive in order to make the potentials of the pair of bit lines BL and BL equal to each other. However, in the above-mentioned condition, the level of the signal line S.sub.1 is nearly equal to the voltage supply V.sub.CC so that the transistors Q.sub.3 , Q.sub.4 and Q.sub.5 are not turned on fully, and therefore the potentials of the pair of bit lines BL and BL are lower than V.sub.CC and are not completely equal to each other. Then, when the clock .phi..sub.1 falls to the L level and the clock .phi..sub.3 rises to the H level, the level of the signal line S.sub.1 rises from V.sub.CC to V.sub.S1 higher than V.sub.CC so that the transistors Q.sub.3, Q.sub.4 and Q.sub.5 are fully turned on and the pair of bit lines BL and BL are both charged up to the voltage supply level V.sub.CC.
By the way, the level V.sub.S1 of the signal line S.sub.1 is determined not only by the voltage supply V.sub.CC and the level V.sub..phi.3 of the clock .phi..sub.3 (in this case, V.sub..phi.3 =V.sub.CC) but is also determined by the push-up capacitor C.sub.1, the capacitor C.sub.2, which is formed along the wiring path of the signal line S.sub.1, and the capacitance C.sub.3 at the gates of the transistors Q.sub.3, Q.sub.4 and Q.sub.5. Thus, the level V.sub.S1 of the signal line S.sub.1 is expressed by the following equation: ##EQU1## In order to charge up the pair of bit lines BL and BL to the voltage supply level V.sub.CC, it is necessary that the second term of the right side of the equation (1) be greater than the threshold voltage V.sub.th of the transistors Q.sub.3, Q.sub.4 and Q.sub.5.
However, even if the condition V.sub.S1 .gtoreq.V.sub.CC +V.sub.th is fulfilled in the case of V.sub.CC =5 V and the pair of bit lines BL and BL are both charged up to the voltage supply level V.sub.CC, the voltage supply V.sub.CC may rise from 5 V to 5.5 V (V.sub.CC +.DELTA.V.sub.CC) after that. In such a case, the value of "V.sub.CC " in the equation (1) will remain 5 V because at this time the clock .phi..sub.1 has already fallen enough so that the transistor Q.sub.1 is turned off. Accordingly, the response of the level of the signal line S.sub.1 to the variance of the voltage supply V.sub.CC depends mainly on the dependence of the clock .phi..sub.3 upon the voltage supply V.sub.CC. An increase in the level of the signal line S.sub.1 can be expressed by the following equation: ##EQU2##
Therefore, even if the clock .phi..sub.3 directly follows the variance of the voltage supply V.sub.CC, the level of the signal line S.sub.1 may increase only a little compared with the increase of V.sub.CC, especially if the capacitor C.sub.2 is relatively large (that is, the path of the signal line S.sub.1 is long). Therefore, if the voltage supply V.sub.CC is changed, it may be that the level V.sub.S1 of the signal line S.sub.1 cannot be higher than the required level (V.sub.CC +V.sub.th). In such a case, the short-circuit between the pair of bit lines BL and BL through the transistor Q.sub.5 is insufficient so that the sense amplifier circuit SA may make an error.
In addition to the voltage supply V.sub.CC, the potentials of the electrodes X adjacent the signal line S.sub.1 forming the capacitor C.sub.2 might be thought of as another factor in relation to the response of the level V.sub.S1 of the signal line S.sub.1. In the semiconductor device of the prior art, the signal line S.sub.1 is formed to run the shortest path between the push-up circuit PU and the precharger circuit PRE, and therefore the adjacent electrodes along the path of the signal line S.sub.1 may be locally adjacent the ground line V.sub.SS, the semiconductor substrate itself, the other signal line, the node in the circuit or the voltage supply line V.sub.CC. However, the proportion of the path of the signal line S.sub.1 adjacent the voltage supply V.sub.CC is generally small, and the potential of the adjacent electrode X as a whole could be thought of as being other than the voltage supply V.sub.CC. Accordingly, in the semiconductor device of the prior art, improvement of the response of the level V.sub.S1 to V.sub. CC according to the adjacent electrode X can not be expected.
Thus, as described above, when the voltage supply V.sub.CC increases by .DELTA.V.sub.CC, the increase of the level V.sub.S1 of the signal line S.sub.1 is only .DELTA.V.sub.S1 in the equation (2), and therefore it is difficult to push up the level V.sub.S1 to a level higher than (V.sub.CC +V.sub.th) after V.sub.CC has increased even if the clock .phi..sub.3 increases by .DELTA.V.sub.CC.